A so-called polymetal gate in which refractory metal such as tungsten is laminated on a polycrystalline silicon film is adopted in order to lower the resistance of the gate electrode of the MISFET.
Meanwhile, a so-called light oxidation treatment for forming a thermal oxide film on a sidewall of the gate electrode is performed in the etching of the gate electrode because a gate insulating film under the gate electrode is also caused to be etched in the etching so that the withstand voltage of the gate insulating film is deteriorated.
For example, the gazette of Japanese Patent Laid-Open No. 2001-36072 discloses a technique for preventing the oxidation of a metal layer by means of protecting the sidewalls of the metal layer composing the polymetal gate.
Also, the gazette of Japanese Patent Laid-Open No. 11-261059 discloses a technique for forming a low-resistance transistor with no metal contamination. According to this technique, the low-resistance transistor without metal contamination is formed by covering the exposed portion of a metal composing the polymetal gate of the transistor with a film of LPCVD-HTO or SiN9, and then by processing a polysilicon film 3 below it.
Also, in “A fully working 0.14 μm DRAM technology with polymetal (W/WNx/Poly-Si) gate” by J. W. Jung et al. in the IEDM 2000 pp. 365-368, disclosed is a cleaning technique using H2SO4 and purified water performed after the etching for a gate electrode made of W/WNx and poly-Si.